1. Field of the Invention
The present invention relates to pulse code modulation (PCM) and is telephone communication systems and receivers, wherein the receiver comprises a switched capacitor filter and more particularly to a receiver including a switched capacitor filter that is switched a predetermined number of times during each synchronization period by a control signal having discrete phase phase shifts.
It is a known fact that a resistor plus capacitor (RC) network is equivalent to one in which each resistor is replaced by a combination of a capacitor and two switch circuits. If C.sub.R is the capacity of the combination capacitor and T the switching period of the switch circuits, then the resistance R equivalent combination is given by EQU R=T/C.sub.R.
(See "Sampled Analog Filtering Switched Capacitors as Resistor Equivalents" by Jerry Caves and al., I.E.E.E. Journal of Solid State Circuits, Vol. SC 12, No. 6, December, 1977). For the operation of filters using switched capacitors for processing an audio-frequency signal, a clock of some 128 to 512 kHz is required.
In PCM systems, two types of synchronization are required, viz: frame synchronization and bit synchronization. Therefore digital transmission and reception terminals of a monolithic "codec+filter" circuit are each comprised of a group of three terminals transmitting or receiving the following signals:
(a) the information bits in the form of a digital sequence from 64 to 2048 kbit/s; PA1 (b) clock bits synchronous with the information bits used for reading out the latter; PA1 (c) a frame synchronization signal permitting identification of the time slot in the frame or multiframe. PA1 utilizing two master clocks respectively synchronous with the time slot defining signals in the transmission and reception directions thus requiring two additional pins and the inclusion of a circuit for the two clocks outside the integrated circuit; PA1 providing a master reception clock synchronous with the received synchronization signal using a phase lock loop, which needs a significant area of the silicon chip (.perspectiveto.15% of the silicon circuit area); PA1 introducing a pulse amplitude-modulated signal smoothing cell between the decoder and the reception filter, which also needs additional area on the silicon chip. PA1 .epsilon.=25.6 Hz and its multiples upto the 156th degree. PA1 .epsilon.=204.8 kHz and its multiples upto the 19th degree. PA1 the relative level of the main lines for a sinusoidal signal with frequencies of respectively 700, 1000 and 1100 Hz; PA1 the signal to noise ratio for various audio signal frequencies in the event of a reception filter control signal frequency F' equal to (1+5.times.10.sup.-5).times.F' where F'=128, 258 or 2048 kHz.
U.S. Pat. No. 3,649,757 issued Mar. 14, 1972 discloses a decoder for receiving PCM signals and frame synchronization signals and connected to an output analog filter.
Over and above these two groups of three terminals, the circuit, in order to function, requires a 2048 kbit/s master clock (case of A coding law).
The control signals for the transmission and reception switched capacitor filters generally result from dividing the master clock. This master clock, unless split into two, can only be synchronous, in the case of the asynchronous codecs, with one of the transmission and reception synchronization signals; it is plesiosynchronous with the other. It will be assumed that the master clock is synchronous with the transmission synchronization signal.
The master clock pulses and consequently the switched capacitor reception filter control signal which is deduced therefrom by division is plesiosynchronous, i.e., close to being synchronous, with the reception synchronization signal.
The lack of synchronism between the reception synchronization signal and the switched-capacitor reception filter control signal gives rise to parasitic spectral lines in the output signal from this filter; the intensity of the spectral lines is somewhat excessive thus making the integrated circuit unusable.
2. Description of Prior Art
These parasitic spectral lines may be avoided by:
The prime object of this invention is to provide a monolithic "codec+filter" integrated circuit in which the parasitic spectral lines are eliminated by employing a perfected frequency divider circuit using an integrated circuit having an additional area much less than than used by a phase lock loop or prefiltering cell.
It will now be shown in relation to FIGS. 1a and 1b how the lack of synchronization between the reception synchronization signal and the switched-capacitor reception filter control signal causes parasitic spectral lines.
In reference to FIG. 1b, a block diagram of a decoder and switched capacitor filter of the prior art, there are provided an input shift register 1, a decoder 2, a switched-capacitor low pass filter 3 with a pass band from 0 to 3,400 Hz, a smoothing cell 4, an output amplifier 5 and the audio-frequency signal output terminal 6. Input register 1 has three inputs 11, 12, 13 that respectively receive the information bits (IB), the clock bits (CB) and the reception synchronization signal (RS). The circuit of FIG. 1b responds to master clock (MC) and reception synchronization signal (RS) to derive control signal (WR), having a frequency F.sub.WR. The transmitter of FIG. 1a responds to master clock (MC) to derive control signal (WT) and time slot defining signal (TS).
The frequencies of signals IB, CB, TS, RS, MC and WR are respectively given by F.sub.IB, F.sub.CB, F.sub.TS, F.sub.RS =F, F.sub.MC, F.sub.WR =F'. By way of an example, it may be assumed that: EQU F.sub.IB =F.sub.CB between 64 and 2048 kHz EQU F.sub.MC =2048 kHz EQU F.sub.WR =F'=256 kHz EQU F.sub.TS =8 kHz EQU F.sub.RS .perspectiveto.8 kHz
In the case of a coder and transmission filter (FIG. 1a), the signals defining the time slots TS and controlling the transmission filter WT are both derived from the master clock by divider 17 dividing the master clock pulse frequency F.sub.MC by 2.sup.N =8, (N=3) and 2.sup.N' =256, (N'=8) so that the frequencies F.sub.TS and F.sub.WT of signals TS and WT are F.sub.MC .div.2.sup.N and F.sub.MC .div.2.sup.N' respectively.
In the case of a decoder and reception filter (FIG. 1b), it is not possible to obtain (RS) and (WR) by division of (MC) since (TS) and (RS) are asynchronous and (TS) has already been made synchronous with (WT).
Let the following expressions be written, where: ##EQU1## where .pi.(t) is a function defined by: ##EQU2## F being the sampling frequency.
The spectrum of the sampled signal is: ##EQU3##
The signal resampled at a frequency F' is: ##EQU4## having a Fourier transform given by: ##EQU5##
First example:
The frequency (nF-kF') falls within the band 0-4 kHz for F=8 kHz; F'=256 kHz; k=1; n=32.
If it is assumed that: EQU F=(1-5.times.10.sup.-5).times.8 kHz EQU F'=(1+5.times.10.sup.-5).times.256 kHz
then we have: EQU .epsilon.=nF-kF'=32(1+5.times.15.sup.-5)8-(1-5.times.10.sup.-5)256 kHz
Second example:
The frequency (nF-kF') falls within the band 0-4 kHz for F=8 kHz; F'=2048 kHz; n=256; k=1
If it is assumed that: EQU F=(1+5.times.10.sup.-5).times.8 kHz EQU F'=(1-5.times.10.sup.-5).times.2048 kHz
then we have: EQU .epsilon.=nF-kF'=256(1+5.times.10.sup.-5)8-(1-5.times.10.sup.-5)2048
In view of the attenuation introduced by the ##EQU6## and the order of magnitude of .epsilon., the calculation may be restricted in the majority of cases for determining the line amplitude in the 0-4 kHz band to: ##EQU7##
Tables 1 and 2 set forth: